In reply to ben@SystemVerilog.us:
property prop_sig_stable(rst, sig);
@(sig)
$changed(sig) |-> $changed(rst);
endproperty : prop_sig_stable
I think that I may have gotten close with the solution above. However, it seems to flag the assertion on the edge of sig following the actual error. Are you aware of a way to insist that an error using the $changed operator will assess on edge of failure?