Assigning a variable in SV Assertion

SystemVerilog
, , ,
1

Hi All,

I want to assign a value to some property variables. I want to assign values to variables wdata, wdata_f0, wdata_f1 as per the following:

wdata = DATA,
if (//condition1)
  wdata_f0 = DATA
else if (//condition2)
  wdata_f1 = DATA

So I tried to replicate the above inside the property as follows:


property data_check (//arguments);
   int wdata = 0;
   int wdata_f0 = 0;
   int wdata_f1 = 0;

    @(clk)
     (//a sequence),
     **wdata = DATA,
      wdata_f0 = (//condition) ? DATA : wdata_f0,
      wdata_f1 = (//condition) ? DATA : wdata_f1**
     )
     |->
      //property sequences
endproperty

But the assertion fails since the logic is not being replicated properly.

2

In reply to atanubiswas:


///In this case wdata_f1 = DATA only if condition1 is wrong and condition2 is correct.
wdata = DATA,
if (//condition1)
wdata_f0 = DATA
else if (//condition2)
wdata_f1 = DATA



//wdata_f1 = DATA if condition2 is correct irrespective of condition1. 
@(clk)
(//a sequence),
wdata = DATA,
wdata_f0 = (//condition1) ? DATA : wdata_f0,
wdata_f1 = (//condition2) ? DATA : wdata_f1
)


//Change it :
//wdata_f1 = (condition2 && !condition1) ? DATA : wdata_f1
3

In reply to Rahulkumar Patel:

Actually condition is of one bit only. Can be either 1 or 0. Can there be issue because of the initialization part i.e int wdata = 0?