Assigning a variable in SV Assertion

SystemVerilog
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2

In reply to atanubiswas:


///In this case wdata_f1 = DATA only if condition1 is wrong and condition2 is correct.
wdata = DATA,
if (//condition1)
wdata_f0 = DATA
else if (//condition2)
wdata_f1 = DATA



//wdata_f1 = DATA if condition2 is correct irrespective of condition1. 
@(clk)
(//a sequence),
wdata = DATA,
wdata_f0 = (//condition1) ? DATA : wdata_f0,
wdata_f1 = (//condition2) ? DATA : wdata_f1
)


//Change it :
//wdata_f1 = (condition2 && !condition1) ? DATA : wdata_f1