Assign statement

SystemVerilog
, , ,
1 
module test;
  reg [2:0]a = 3'b011;
  reg[2:0] b = 3'b010;
  reg[2:0] c = 3'b110;
  reg[2:0] out;
  
  
  initial begin
    assign out = (a == b) ? 1:0;
    $display("out = %b",out);
  end
endmodule

This code is working fine!
can we write assign statement in initial begin?

2

In reply to m_v:

Section 10.3 of the LRM discusses continuous assignments, and section 10.6 discusses procedural continuous assignments. You should read both sections and you can determine how your code is functioning.

3

In reply to cgales:

Hi, i also checked same question on verification academy :-https://verificationacademy.com/forums/systemverilog/drive-reg-using-continuous-assign, Problem here is that in Verilog we can not write reg type variable on the L.H.S of the assign statement.

Verilog there are 3 types of assignments 1.continuous assignment 2.procedral assignment 3. procedural continuous assignment, and for continuous assignment at the L.H.S must be a net it can not be a reg type, but when it is procedural continuous assignment then it is valid to have reg at L.H.S but we can not write net.

System Verilog also has this 3 types but here with continuous assignment when we write reg at L.H.S it is valid and net type also valid, with the procedural continuous assignment the L.H.S must be reg, wire is invalid.

Also one observation is that in system Verilog when you drive net with assign statement then the display is executed first(out = x) and then the assignment to the net is done if i put #0 delay as per the code the display will be executed in inactive region and the new value will be displayed(out = 1) and with reg it is working fine no need to put #0 delay, i am not able to find out why this is happening?

module test;
  reg a = 1'b1;
  wire out;
  
  assign out = a ? 1:0;
  
  initial begin
    #0 $display("out = %b",out);
  end
endmodule

Thank you.

4

In reply to m_v:

It is a time 0 race condition. Both results are valid.

1 Like