Assign a range of number in unpacket array

SystemVerilog
1

Hi : I am not sure how to put a range of data inside of unpacked array, or q[$], dynamic array.
for example int array = '{ 'h1, 'h6, 'h20:'h2f};
i will get error on 'h20:'h2f

thanks

2

There is no syntax to get a range of numbers in an assignment directly, but you can create a function to do it for you.

module top;
   int A1[], Q1[$],F1[10];
   typedef int DA_t[];
   function automatic DA_t range(int first, last);
      int      index;
      if (first < last)
	begin
	   range = new [last-first+1];
	   for(int i=first;i<last+1;i++)
	     range[index++] = (i);
	end
      else
	begin
	   range = new [first-last+1];
	   for(int i=first;i>last-1;i--)
	     range[index++] = (i);
	end 
      
   endfunction : range

   initial begin
     A1 = {32'h1, 32'h6, range('h20,'h2f)};
     Q1 = {'h1, 'h6, range(30,25),range(5,1) };
     F1 = {'h1, 'h6, range('h20,'h27)};
      $display("%p",A1);
      $display("%p",Q1);
      $display("%p",F1);
   end
endmodule : top
3

Thanks Dave.
It helps. but I am thinking if it makes sense to you if Systemverilog LRM can support it in next release. I think it is a fundamental but it is very useful. In my case, i have a router fabric, like
my_port = '{ x }
my_other_ports = '{ … }
without this feature, i have to either use the methode you provided or manully write it.

just my opinion.
thanks

4

In reply to aming:

There already is an enhancement request, but it will miss the next revision, due out by the end of the year.

5

Thanks Dave. unfortunatelly, it does not get compiled in VCS.