Thanks Dave.
It helps. but I am thinking if it makes sense to you if Systemverilog LRM can support it in next release. I think it is a fundamental but it is very useful. In my case, i have a router fabric, like
my_port = '{ x }
my_other_ports = '{ … }
without this feature, i have to either use the methode you provided or manully write it.
just my opinion.
thanks