In reply to Manoj J:
With this assertion
ap_siga2siga: assert property(@(posedge clk) sig_a && !count |=>
!sig_b throughout sig_a[->1]);
always@(posedge clk)
begin
if(sig_a && (count == 0))
count <= 1;
else if(sig_a && count == 1)
count <= 0;
end
The imlied requirements for this would be:
Upon a first occurrence of sig_a, sig_b remains at 0 until the next occurence of sig_a.
That 2nd occurrence of sig_a will not restart this sig_b check until a third occurrence of sig_a.
Is that really the requirements you want? I may be wrong, but intuitively, I would think that you have another triggering condition for that first occurrence of sig_a, maybe something from a combinational logic other than sog_a, or from a state machine. The reason I say that is that assertions should reflect requirements. The requirement that I implied from your code is odd. I would have expected something like:
When CONDx, then starting from the next (or current) cycle sig_b remains low until sig_a.
ap_siga2siga: assert property(@(posedge clk) $rose(CONDx) |=> // |-> ok here if needed
!sig_b throughout sig_a[->1]);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy