In reply to ben@SystemVerilog.us:
[3] On your " if(a && (count == 0))" did you mean “a” or “sig_a”?
Sorry for the mistake. It is
always@(posedge clk)
begin
if(sig_a && (count == 0))
count <= 1;
else if(sig_a && count == 1)
count <= 0;
end