Assertions

SystemVerilog
,
1

hi all,
I am new to Systemverilog,is assertion used in systemverilog class.

Thanks
Natarajan.NA

2

You may use immediate assertions in class.
Though properties and sequences are supported only at modules / interfaces.

3

See at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
avaiable in the verification-horizons October-2013-volume-9-issue-3
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3

Assertions Instead of FSMs/logic for Scoreboarding and Verification
by Ben Cohen, Accellera Systems Initiative, VhdlCohen Publishing
Monitors, scoreboards, and verification logic are typically implemented using FSMs, logic, and tasks. With UVM, this logic is hosted in classes. This article demonstrates another option of implementing some monitors and scoreboards using SVA assertions hosted in SV interfaces. The basic concept involves using assertion statements along with functions, called from sequence match items, to collect the desired scoreboard information, to compare expected results to collected data, and to trigger covergroups. This concept is demonstrated using a UART transmitter as the DUT. Since the purpose of this model is to demonstrate the use of assertions to emulate verification logic, the driver for this DUT originates directly from a top level module. To demonstrate the difference between an assertion-verification solution versus a monitor/scoreboard-solution in classes, a monitor class was implemented. Assertions Instead of FSMs/logic for Scoreboarding and Verification

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
4

In reply to Beeri:

hi Beeri,
Can you give simple example for immediate assertion using class.

5

In reply to arasupotri.natarajan90:

You can put an immediate assertion wherever you can insert an “if” or “case” statement; thus, in a class, it would be in a function or a task. For example:

class test_asn;
    int a=1; 
    rand bit[7:0] b, c=0, d; 
    // test
    task tbc( );
        ap_abc: assert (b==c) else $display("%m b = %b, c=%b", b, c);
    endtask : tbc
    
endclass : test_asn

module m_asn;
    test_asn t1; 
    initial begin : i1
        t1=new(); 
        t1.b=8'b0000_0001;
        t1.tbc(); 
    end :i1

endmodule :m_asn

However, concurrent assertions cannot be inserted in classes. My paper October 2013 | Volume 9, Issue 3 | Verification Academy demonstrates how you can effectively use concurrent assertions with class variables by first copying those variables into an SV interface. Typically, those variables wil used in combination with interface signals to do scoreboard type of verification.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
    …