See at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
avaiable in the verification-horizons October-2013-volume-9-issue-3
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3
Assertions Instead of FSMs/logic for Scoreboarding and Verification
by Ben Cohen, Accellera Systems Initiative, VhdlCohen Publishing
Monitors, scoreboards, and verification logic are typically implemented using FSMs, logic, and tasks. With UVM, this logic is hosted in classes. This article demonstrates another option of implementing some monitors and scoreboards using SVA assertions hosted in SV interfaces. The basic concept involves using assertion statements along with functions, called from sequence match items, to collect the desired scoreboard information, to compare expected results to collected data, and to trigger covergroups. This concept is demonstrated using a UART transmitter as the DUT. Since the purpose of this model is to demonstrate the use of assertions to emulate verification logic, the driver for this DUT originates directly from a top level module. To demonstrate the difference between an assertion-verification solution versus a monitor/scoreboard-solution in classes, a monitor class was implemented. Assertions Instead of FSMs/logic for Scoreboarding and Verification
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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