Assertions in Interface

UVM
,
1

Hi,

As per the UVM standards ,concurrent assertions cannot be implemented in Class based objects.

How to implement concurrent assertions in Interface can anybody explain with example?

~Taahir

2

In reply to syed taahir ahmed:

Correct; interfaces are are static, thus allow concurrent assertions. There are tons of examples if you just google it.

3

In reply to bmorris:

In reply to syed taahir ahmed:
Correct; interfaces are are static, thus allow concurrent assertions. There are tons of examples if you just google it.

i did googled it,not found any proper full fledged example,can you please point me the link?

~Tashir

4

In reply to syed taahir ahmed:

http://lmgtfy.com/?q=example+of+assertion+inside+systemverilog+interface

5

In reply to dave_59:

Thanks Dave,able to implement assertions in interface.