what if we want to evaluate Asynch. Properties ( Specifically if you don’t have Clock ). How to write property clock and its Definition.
In reply to ben@SystemVerilog.us:
Like…How to write assertions for design without clock e.g Asynchronous FIFO.
What should the pre-requisites in mind before writing the assertions & the approach towards anything asysnchronous?
And can you please explain how sampling one signal(NOT a clock signal) with respect to other signal work?
In reply to Samruddh:
In reply to ben@SystemVerilog.us:
Like…How to write assertions for design without clock e.g Asynchronous FIFO.
What should the pre-requisites in mind before writing the assertions & the approach towards anything asysnchronous?
Are you talking about asynchronous logic with no clock? It was a long time ago that I took a class in async logic, and the one thing I remember is that stability is very tricky!
I asked ChatGPT this, and it gave me a good response. I’ll follow this with more answers to your questions.
[Ben] What is asynchronous logic?
[ChatGPT] Asynchronous logic refers to a digital design approach where the components of a circuit do not rely on a common clock signal for synchronization. In synchronous digital systems, a clock signal is used to synchronize the operation of various components, ensuring that different parts of the system change their states at specific, coordinated times. In contrast, asynchronous logic operates without a global clock, allowing individual components to change state independently as soon as their inputs meet certain criteria.
**Key characteristics of asynchronous logic** include:
**No Global Clock**: Unlike synchronous systems that use a centralized clock to coordinate operations, asynchronous logic circuits do not have a global clock signal. Each element operates independently based on local timing.
**Handshaking Protocols**: Asynchronous circuits typically use handshaking protocols to manage communication between different components. Handshaking involves a set of signals exchanged between components to indicate readiness for data transfer, enabling synchronization without a global clock.
**Variable Timing**: Asynchronous circuits allow for variable timing in data processing. The completion of a computation or operation is not tied to a fixed clock cycle; instead, it depends on the actual time it takes for the logic elements to perform their tasks.
**Reduced Power Consumption**: Asynchronous logic can offer advantages in terms of power consumption because components only operate when needed. In synchronous systems, even when a component has nothing to do, it often toggles at the clock rate, consuming power.
**Complex Control Logic:** Asynchronous circuits may require more complex control logic to manage the timing and handshaking between different components. This complexity can make asynchronous design more challenging than synchronous design in some cases.
**Avoidance of Clock Skew Issues**: Asynchronous logic can potentially eliminate issues related to clock skew, which is the variation in arrival times of the clock signal at different components. This is because asynchronous circuits don't rely on a common clock signal.
**Asynchronous logic is often used in specific applications** where its benefits, such as reduced power consumption and avoidance of clock skew issues, outweigh the challenges associated with its design complexity. Examples of applications include certain low-power and high-reliability systems. However, synchronous logic remains the dominant approach in most digital designs due to its well-established methodologies and ease of implementation.
[Ben] If my memory is correct, an async logic relies on states stored in latches instead of clocked FF. Thus, state changes are based on the current states and inputs, and any glitch can give you nightmares. SVA is based on events, which can be clocking events or state changes.
Using it for async logic is tricky because of the sampling. I tried this:
bit[3:0] stA, stB, stC;
bit a, b, c;
// @rise(a) the sampling of stA==4'b0001.
// stA will then toggle to a value of 4'0010 and that causes b to toggle after some delay.
ap_stA2B: assert property(@(a==1) stA=4'b0001 |-> @(b==1) stA==4'b0010);
// note: in the antecedent, stA is sampled with (@(a==1).
// in the consequent, stA is sampled with @(b==1)
And can you please explain how sampling one signal(NOT a clock signal) with respect to other signal work?
As explained above, it is tricky.
ChatGPT on Async Fifo:
key points about Asynchronous FIFOs:
Dual-Ported: An asynchronous FIFO typically has two ports—one for writing data and one for reading data.
Buffering: The FIFO acts as a buffer, storing data temporarily until it can be read by the receiving side.
Handshake Signals: Asynchronous FIFOs use handshake signals such as “write enable,” “write pointer,” “read enable,” and “read pointer” to coordinate the transfer of data between the read and write sides.
Different Clock Domains: Since the read and write sides may be operating with different clock signals, the asynchronous FIFO includes logic to synchronize the data transfer and prevent issues such as data loss or corruption.
Empty and Full Conditions: The FIFO can signal when it is empty (no data to read) or full (no space to write) to help manage data flow.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.