I am trying to assert a behavior when a slave is asserted on the slave interface, the status should be captured in a register.
The slave interface operates at a slower clock while the register capture is happening inside the logic which is synced to a faster clock. As I understood, delays greater than 1 is not allowed, how can I achieve this? The register capture can happen say until 10 faster clock cycles.
The slave interface operates at a slower clock while the register capture is happening inside the logic which is synced to a faster clock.
As I understood, delays greater than 1 is not allowed, how can I achieve this?
?? what does that mean? 1 what? cycle? which cycle?
The register capture can happen say until 10 faster clock cycles.
property p1;
disable iff(reset_n == 1'b0)
@(posedge slow_clk) $rose(sig1) |->
@(posedge fast_clk) // switching to the very closer fast clock edge
// of the slow clock. can be the same edge if both at same edge
##[0:10] $rose(reg_slverr); // 0 to 10 of the fast clock
endproperty
Ben Cohen Ben@systemverilog.us
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You suggested solution works. I think I got confused with the term concatenation operator explained in:
sv1800’2017 16.13.1 Multiclocked sequences
Multiclocked sequences are built by concatenating singly clocked subsequences using the single-delay concatenation operator ##1 or the zero-delay concatenation operator ##0. The single delay indicated by ##1 is understood to be from the end point of the first sequence, which occurs at a tick of the first clock, to the nearest strictly subsequent tick of the second clock, where the second sequence begins. The zero delay indicated by ##0 is understood to be from the end point of the first sequence, which occurs at a tick of the first clock, to the nearest possibly overlapping tick of the second clock, where the second sequence begins.
Now I am starting to realize that the limitation set by this rule is actually on the concatenation of sequences part only, not any other cycle delay like ##[0:10] in this case. Correct me if I am still wrong…