In reply to RB87:
The slave interface operates at a slower clock while the register capture is happening inside the logic which is synced to a faster clock.
As I understood, delays greater than 1 is not allowed, how can I achieve this?
?? what does that mean? 1 what? cycle? which cycle?
The register capture can happen say until 10 faster clock cycles.
property p1;
disable iff(reset_n == 1'b0)
@(posedge slow_clk) $rose(sig1) |->
@(posedge fast_clk) // switching to the very closer fast clock edge
// of the slow clock. can be the same edge if both at same edge
##[0:10] $rose(reg_slverr); // 0 to 10 of the fast clock
endproperty
Ben Cohen
Ben@systemverilog.us
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