Assertion to check x or z when signal toggles instead of every clock tick

SystemVerilog
, , ,
2

In reply to Dilsya:
The issue you have with **assert property (@(a)!$isunknown(a))**is that “a” is sampled in the Preponed Region when “a” changes. Thus, if “a” goes from “1” to “X”, the sampling value is a “1” and thus $isunknown is false. You need the sampling to be in the Active Region.
Use the always with an immediate assertion.


module top;
  logic a=1'bX;
  event e;
  always @(a) begin 
    $display("%t change in a", $realtime);
    a_unknown: assert (!$isunknown(a)) else  $display("%t Is unknown in a", $realtime);
    -> e; 
  end

 // "a" is sampled in the Preponed Region! 
  x_prop_on_d_assert : assert property (@(a)!$isunknown(a)) else $display("%t proprIs unknown in a", $realtime);; 
  initial begin 
    a=1'bX; 
    #20 a=1; 
    #20 a=1'bZ; 
    #20 a=0;
    #20 a=1'bX;
    #20 a=0;
    #20 a=1;
    #20 a=0;
    #30; 
   end 
endmodule 
                  20 change in a
#                   20 proprIs unknown in a
#                   40 change in a
#                   40 Is unknown in a
#                   60 change in a
#                   60 proprIs unknown in a
#                   80 change in a
#                   80 Is unknown in a
#                  100 change in a
#                  100 proprIs unknown in a
#                  120 change in a
#                  140 change in a

1853×859 163 KB

1853×859 163 KB

Ben Cohen
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