Verification Academy
Assertion to check without using any clock, if signal A is high signal B must be high
SystemVerilog
SystemVerilog
,
Assertion-system-verilog
,
SVA
,
assertion
,
glitch
dave_59
February 7, 2020, 4:18pm
3
In reply to
shals
:
If you truly mean “for all time”
assert final (A->B);
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