Assertion to check when any bit of the byte enable signal is high corresponding bits in the check signal shouldn't have X in that byte

SystemVerilog
,
1

Greetings,

I would like to add an assertion to check for a byte enable signals if any bit is high in that signal, I should not get Xs in corresponding bits of the check signal

I am not able to form a logic or find any head start on how to achieve it.
eg.
Byte_enable_signal[15:0]
check_signal[127:0]
In words,

if Byte_enable_signal[15:0] = 0xb0000000000000001 -------> check signal shouldn’t contain any Xs in the last byte(0x00000000000000X)

If Byte_enable_signal = 101----> then last 1st and 3rd byte should not have Xs. I don’t care if 2nd byte has Xs or not.

I hope I made the question clear. Can someone please guide me here.

2

In reply to Spriyada29:

Not sure if there is a more efficient way to do it but here is one way,

      property x_check0;
        if (enable[0])
          !$isunknown(check[7:0]);  //or ^(check[7:0]) !== 1'bx ;
      endproperty
      property x_check1;
        if (enable[1])
          !$isunknown(check[15:8]);
      endproperty
      property x_check15;
        if (enable[15])
          !$isunknown(check[127:120]);
      endproperty

Separate the bits out and check each individually.