In reply to ben@SystemVerilog.us:
Basically, How can I check toggling of signal “c” when frequency of signal “c” is same as “clk”?
“$changed” will get same sampled value of c at each posedge of clk even though “c” is toggling.
$changed assertion will fail if “c” is toggling with same frequency of clk or remains stable, hence does not matter.
So, cannot use $changed.
One approach for solution would be as follows
property p;
logic v,o;
@(posedge clk)
(a > 2, v = c) |-> if (b)
(@(negedge clk) (1, o = c) |-> (v == o)) // not sure why always(c) is not working
else
(@(negedge clk) (1, o = c) |-> ( v != o));
endproperty
But above solution assumes both “c” and “clk” have same frequency but not valid if signal “c” is having different frequency than clk. Is there any logic/construct that checks just toggling of signal without dependency on assertion clock.