In reply to rohithgm:
I don’t fully understand your requirements. However, I have a suggestion that can get you started on the right path. That suggestion makes use of concepts explained in my paper
SVA Alternative for Complex Assertions The paper was published at Verification Horizons - March 2018 Issue | Verification Academy
Your solution would look something like
$rose(a) |-> (1, my_task(b, c));
task automatic my_task(bit b, c);
// here you can use # delays, wait statements, @ (posedge clk),
// fork other tasks, or whatever you need to verify your requirements
endtask
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- Verification Horizons - March 2018 Issue | Verification Academy
- SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
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