Assertion to check signal change only once(1->0->1) between 2 events

SystemVerilog
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12

In reply to mlsxdx:

Using intersect e[->1] instead of within e[->1] require that the rising edge of b strongly related to rising edge of e.
In my application, the rising edge of b and rising edge of c are not strict related. In other words, when b go high, it could be many clock cycles, then e go high. If this is the case, do you have any suggestion to attack the problem?
(##1 $fell(b)[->1] ##1 b[=1] ##1 !b) intersect e[->1]
This requires that b go low aligning with e go high by using intersect. In my case, b from high to low is after e go high.


// If b cannot fall after the rise then 
(##1 $fell(b)[->1] ##1 b[->1] ##1 b[*0:$]) intersect e[->1]
// if b is a pulse then 
(##1 $fell(b)[->1] ##1 $rose(b)[=1]) intersect e[->1]
// equivalent to  
(##1 !fell(b)[*0:$] ##1 $fell(b) ##1 !$rose(b)[*0:$] ##1 $rose(b) ##1 !$rose(b)[*0:$]) 
  intersect e[->1]