In reply to ben@SystemVerilog.us:
In reply to mlsxdx:
The (##1 $fell(b)[->1] ##1 b[=1] ##1 !b) intersect e[->1];
says that between b and e there must be at least 1 !b; there can be more.
Tou could also write a separate assertion like
not(b && e);
Hi Ben,
Using intersect e[->1] instead of within e[->1] require that the rising edge of b strongly related to rising edge of e.
In my application, the rising edge of b and rising edge of c are not strict related. In other words,
when b go high, it could be many clock cycles, then e go high. If this is the case, do you have any suggestion to attack the problem?
(##1 $fell(b)[->1] ##1 b[=1] ##1 !b) intersect e[->1]
This requires that b go low aligning with e go high by using intersect. In my case, b from high to low is after e go high.