In reply to ben@SystemVerilog.us:
Ben,
You are right the spec is not complete, if req comes anywhere else other than between start and eop than ack is expected at very next clock. I am validating this using interface monitor and assertion is not required to cover this scenario.
There is no dependency of eop on req, eop will come no matter what for each start, my test case sequence end condition is to receive eop. Bounded assertion for this interface is difficult as cycles consumed between start and eop depends on lot of factors which changes dynamically during simulation like random read response delays.
Regards,
Rohit