Assertion to check number of clock pulses

SystemVerilog
7

In reply to Srini @ CVCblr.com:
Your figures show that clk is a master clock and sck is a derived divde-by-two clock and is not a separate async clock. If that is the case, then the following should work
See diagrams below.


 ap_cs_n: assert property(  
        @(posedge clk)  $fell(cs_n) |-> 
            (##2 sck && !cs_n ##2 !sck && !cs_n)[*16] ##2 $rose(cs_n));

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Ben Cohen
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