In reply to gv_bing:
Simpler with modeling code - untested below.
// 1. cs_n is a synchronous signal clocked at the posedge of clk
always @(posedge clk)
if (!cs_n) sclk_count <= 0;
// 2. cs_n goes low
// 3. count sck for 16 cycles
always @(posedge sclk) // assume 16 posedge
sclk_count++; // lazy, use <= + 1
// 4. cs_n goes high
a_chk_sclk_16 : assert property
( @(posegde clk) $rose (cs_n) |-> sclk_count == 16 );
// Am sure you will need to tweak the NBA/BA/count by 1-2 to get it right
Good Luck
Srini
www.verifworks.com