Assertion to check number of clock pulses

SystemVerilog
5

In reply to gv_bing:


/* there are two clocks -- clk and sck
1. cs_n is a synchronous signal clocked at the posedge of clk
2. cs_n goes low
3. count sck for 16 cycles, cs_n stays low <--- ADDED this 
4. cs_n goes high*/
     ap_cs_n: assert property(  
        @(posedge clk)  $fell(cs_n) |-> 
            @(posedge sck) !cs_n[*16] ##0 @(posedge clk) $rose(cs_n));
// note that when cs_n is high sck is always 0 
    ap_cs_nHI: assert property(  
              @(posedge clk)  cs_n |-> sck==1'b0);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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