In reply to ben@SystemVerilog.us:
In reply to gv_bing:
Your requirements were not very clear. I interpreted them to be:
Following a fall of cs_n, cs_n remains at zero for 16 cycles, and then rises to a logical one. cs_n is a synchronous signal clocked at the posedge of sck.
ap_cs_n: assert property(
@(posedge sck) $fell(cs_n) |=> !cs_n[*16] ##0 $rose(cs_n));
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- Free books: Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb - Papers:
- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2 - SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
For training, consulting, services: contact http://cvcblr.com/home.html =>
Hi Ben, when I click download profile, file not found (404 error) occurs. What should I do? Thanks~