Assertion to check if A does not rise between pulse B and Pulse C

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben,

   If in between B and C there may be any number of clock cycles like [1:$] in a given simulation but A should not be become high in between B and C.

In that case how your code looks like?

Regarding “reject_on”

I don’t know about this.As per our requirement we should reject property when A is high right ?
in that why you have written like "assert property(reject_on (!a) " it should be “assert property(reject_on (a)”.

Could you please explain ?

Does below cod work ?


assert property (@(posedge clk) $rose(b) |-> (reject_on(a) c[1:$]);

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