Assertion to check for the toggle (0->1) of a signal

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben,

I used the below code you had suggested to check the toggle of a signal.

assert_check: assert property (@(posedge clk) s_eventually $rose(sig1));

But I an facing an issue with this.

Suppose, 0 to n clock cycles are there in my simulation and the $rose(sig1) is coming after x clock cycles.

Then this assertion is showing errors for the (n-x) clock cycles, because after x clock cycles also it is expecting $rose(sig1) to come, but ideally it should check only once of $rose(sig1) throughout the signal.

Please suggest.

thanks & regards,
sanjoy