Assertion to check for the toggle (0->1) of a signal

SystemVerilog
,
4

In reply to sanjay864u:

QuestaSim DOES support the s_eventually; you must have an older version.
Talk to your support group. In any case, you can do this:

assert_check: assert property (
     @(posedge clk) strong(##[1:$] $rose(sig1)) );

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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