Assertion question

SystemVerilog
1

Hi Dave,

After reading your blog on program blocks, I am stuck with your Quiz. How can you get an assertion pass and fail in the same time slot? For which I don't have an answer and would be interested to know your thoughts on this. I am sure many users would want to know this.

Also, you mentioned about a blog on virtual interfaces. Could you point me to that ?

In fact, I would be interested to read all the blogs that you posted so far. Is there a link to access all of them ?

Thanks,
Madhu

2

How can you get an assertion pass and fail in the same time slot?

Dave was talking about immediate assertions. Here you can use the deferred immediate assertions to be safe. Concurrent assertions don’t have that issue.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Hi Ben,

Could you please explain why the problem comes with immediate assertion only ? What exactly do you mean by “deferred immediate assertion”. Did you mean delay the assertion ?

Regards,
Madhu

4

In reply to mseyunni:

1800 explains deferred assertions in section 16.4
Basically, the reason you can have multiple action block messages in an immediate assertion is the fact the action block is fired at the time the assertion is called, but because signals may change at different timing regions, you’ll get multiple firing of the assertion in the same time step. See this link extracted from my book on timing regions.

//example of possible conflict 
// from 1800, page 335
// The following example shows how deferred assertions might be used to avoid 
// undesired reports of a failure due to transitional combinational values 
// in a single simulation time step:
assign not_a = !a;
always_comb begin : b1
  a1: assert (not_a != a);
  a2: assert #0 (not_a != a); // Should pass once values have settled
end

When a changes, a simulator could evaluate assertions a1 and a2 twice—once for the change in a and once
for the change in not_a after the evaluation of the continuous assignment. A failure could thus be reported
during the first execution of a1 . The failure during the first execution of a2 will be scheduled on the
process’s deferred assertion report queue. When not_a changes, the deferred assertion queue is flushed due
to the activation of b1 , so no failure of a2 will be reported.

See 1800: 16.4.1 Deferred assertion reporting

Ben Cohen http://www.systemverilog.us/

  • SystemVerilog Assertions Handbook, 3rd Edition, 2013
  • A Pragmatic Approach to VMM Adoption
  • Using PSL/SUGAR … 2nd Edition
  • Real Chip Design and Verification
  • Cmpt Design by Example
  • VHDL books
5

In reply to ben@SystemVerilog.us:

Thank you Ben.