In reply to ben@SystemVerilog.us:
Hi Ben,
Could you please explain why the problem comes with immediate assertion only ? What exactly do you mean by “deferred immediate assertion”. Did you mean delay the assertion ?
Regards,
Madhu
In reply to ben@SystemVerilog.us:
Hi Ben,
Could you please explain why the problem comes with immediate assertion only ? What exactly do you mean by “deferred immediate assertion”. Did you mean delay the assertion ?
Regards,
Madhu