In reply to ben@SystemVerilog.us:
Hi Ben ,
I was trying to solve it using $past(). It’s not throwing any error on eda-playground , but it’s not displaying what I want.
module m;
bit clk, vld, req, ack, rst_n;
initial forever #10 clk = !clk;
property p1;
int count = 0;
@(posedge clk) disable iff(!rst_n)
$rose(req) |=> ((vld != $past(vld),count++)[->0:$] ##1 ($rose(ack),$display("count is:%0d and time is:%0t",count,$realtime))) ##0 (count >= 10);
endproperty
assert property (p1);
initial begin :init1
$dumpfile("dump.vcd"); $dumpvars;
repeat (1) @(posedge clk);
req <= 1'b1;
repeat(2) begin :rpt1
@(posedge clk);
vld<= 1; req<=0; ack <=0;
@(posedge clk);
vld<= 0; req<=0;
repeat(2) @(posedge clk);
end :rpt1
ack <=1;
@(posedge clk) req<=1; ack<=0;
repeat(3) begin
@(posedge clk);
vld<= 1; req<=0; ack <=0;
@(posedge clk);
vld<= 0; req<=0;
repeat(2) @(posedge clk);
end
ack <=1;
repeat(2) @(posedge clk);
$finish;
end
endmodule
-Is it right process or Do I need to think of alternative ?