In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for providing the detailed solution, I tested the model for valid cycles less than 2 or 0 and none of the assertions are reporting failure. The relationship requirement between these 3 signals were that vld must occur atleast 10 (or 2 in your model) times between req and ack. To satisfy this I used the strong in consequent but it doesn’t work as expected. Can you please help on how to solve this?
Regards,
Rohit