Assertion on req and gnt signals

SystemVerilog
,
10

In reply to ben@SystemVerilog.us:

How about having the check in the monitor instead of assertions ?

class  monitor; 
  virtual intf if1; 
  real reqque[$],gntque[$]; 
  function new (virtual intf if1);
    this.if1=if1; 
  endfunction 
  task load(); 
    forever begin 
      @(posedge clk); 
      if(if1.req) 
        reqque.push_back($time); 
      if(if1.gnt) begin 
        gntque.push_back($time); 
        check(); 
      end 
    end 
  endtask 
  task check(); 
    real t1,t2; 
    t2=gntque.pop_front(); 
    t1=reqque.pop_front(); 
    if( t2-t1 > 5 ) 
      `uvm_error("gnt violated the timing");
  endtask 
  task run(); 
    load(); 
  endtask
endclass