Assertion on conditional statements

SystemVerilog
2

In reply to Anudeep J:
It is best to express this in two assertions instead of one.
In general, multiple smaller assertions are preferred as they are easier to write and understand. Thus, usin “a” instead of your “out”


// a) a is asserted immediately if in=1.
// b) a is -de-asserted after n cycles if in=0;
   let n=20;
   int m=20; 
   ap_aON: assert property(@ (posedge clk)  $rose(in) |-> a);  

   ap_aOFF_staticInfinite: assert property(@ (posedge clk) $fell(in) |=> !a[->1]);  // n== infinity 
   ap_aOFF_staticN: assert property(@ (posedge clk) $fell(in) |=> ##n !a); 
      
   import sva_delay_repeat_range_pkg::*; // see the link to the package below 
   // the import statement should be below the module declaration 
   ap_aOFF: assert property(@ (posedge clk) $fell(in) |=> q_dynamic_delay(m) ##0 !a);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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