Assertion for toggle coverage on a bus

SystemVerilog
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1

Hello,

Is there a way to check for toggle on each bit of a 32-bit bus (bus[31:0])? I can think of checking for toggle on individual bits but can’t figure out a way to check for toggle on the whole bus. $past will check to see if current value is not equal to past value, but will not help with toggle. Will $changed work? Does $changed accept a bus/vector or only a scalar? For example,

property tcheck;
@(posedge clk) $rose(tglc) |=> $changed(bus[31:0]);
endproperty

OR

tP: assert property (@(posedge clk) ##1 $changed(bus);

Thanks.

2

In reply to a72:

Hello,
Is there a way to check for toggle on each bit of a 32-bit bus (bus[31:0])? I can think of checking for toggle on individual bits but can’t figure out a way to check for toggle on the whole bus. $past will check to see if current value is not equal to past value, but will not help with toggle. Will $changed work? Does $changed accept a bus/vector or only a scalar? For example,
property tcheck;
@(posedge clk) $rose(tglc) |=> $changed(bus[31:0]);
endproperty
OR
tP: assert property (@(posedge clk) ##1 $changed(bus);
Thanks.

Figured out. $changed takes a vector and works. Here’s the complete solution.

module cdetect;

logic tglc, clk;
logic [31:0] bus;

property cd;
@(posedge clk) ((tglc),$display($stime,“tglc fired”)) |=> $changed(bus[31:0]);
endproperty

cdp: assert property (cd) else $display($stime,“FAIL”);

initial
begin
tglc = 0; clk=0; bus = 32’hffff_0000;
#1; tglc = 1;
@(negedge clk); bus = ~bus;
@(negedge clk); bus = ~bus;
@(negedge clk);
#100 $finish;
end

always #10 clk = ! clk;

initial $monitor($stime,,,"clk = %b bus = %b tglc=%b",clk, bus,tglc);

endmodule