In reply to alexkidd84:
Your requirements are not clear; I believe that this is what you are trying to express:
At (fell(a) && !b) then starting from the next clock “c” holds the value it had at the fell(a)
until a rose(a). At the rose(a), “c” can change value.
//my purpose is to check that 'c' is stable since a fell down (and b is low)
//and until a goes high again.
property p_cstable;
bit v;
@(posedge clk) disable iff (!reset_n)
($fell(a) && !b, v=c )|=> c==v s_until $rose(a);
endproperty
ap_c_stable: assert property(p_cstable);
If this is not your requirements, then please re-express them again.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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