Assertion for invalid clock behavior with respect to clock request and acknowledge

SystemVerilog
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2

In reply to ChChee:
Your requirements are ambiguous, but reading through the lines, you seem to be saying that upon a request you did not receive an ack though there were clocks.

differentiate clock need at least an ack pulse throughout the error section.

What does that mean?
What was your assertion? I see it as:


ap_req_ack: assert property(@ (posedge clk) $rose(req) |-> 
                                  ##[1:8] ack ); // guessing at that 8

Ben Cohen
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