Assertion for D Flip Flop

[navjeet1503]

Hi everyone, I was trying to write assertion for my D-Flip Flop code but I am getting “assertion error” for my second property. My DFF is Asynchronous active high reset. Here is my code :
/////////////////////////////////////////////////ASSERTION LOGIC////////////////////////////
property check_reset;
@(reset)
reset |-> q==0;
endproperty

property check_d;
@(posedge clk)
disable iff (reset)
(q ==$past(d));
endproperty

acheck_reset:assert property(check_reset);
acheck_d: assert property(check_d);
////////////////////////////////////////////DFF LOGIC///////////////////////////////////////////
always@(posedge clk,reset)
begin
if(reset)
begin
q <= 4’b0000;
end
else if (!reset)
q<= d;
end
//////////////////////////////////////////////////////////////////////////////////////////////

[ben2]

In reply to navjeet1503:
1800 16.9.3 Sampled value functions states: If there do not exist k strictly prior time steps in which the event ev iff expression2 occurred, then the value returned from the $past function is the default sampled value of expression1 (see 16.5.1).
Thus, on the very first clocking event, $past(d) is the default value of d.
Therefore, in the very first clocking event, (q ==$past(d)) will fail if q=='X.
To fix this, do the following

property check_d;
  @(posedge clk) disable iff (reset)
   (##1 q ==$past(d));
endproperty 

Meaning that every assertion test of q is delayed by 1 clock. In other words, at clock 3, q is tested at clock 4, and its value should be the value of d at clock 3.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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[navjeet1503]

In reply to ben@SystemVerilog.us:

Thank you Ben for a quick response. I got your point.

Regards
Navjeet