Assertion for counting clock cycles during reset pulse

SystemVerilog
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5

In reply to spoiled rabbit:

Is your motivation to ensure reset is active long enough? If yes, consider below pseudo-code (not fully tested, will have corner case issues).


 always @ (posedge clk) begin
    if (reset) begin
      rst_cyc_count <= 0;
    end
    else begin
      rst_cyc_count <= rst_cyc_count + 1;
    end
  end
 
  a_rst_cyc_chk : assert property (
    @ (posedge clk) 
    ##1 $rose(reset) |-> (rst_cyc_count > 2) );