In reply to ben@SystemVerilog.us:
Let me simplify and ignore other scenarios. I want the assertion to check for refclk to be gated when req and ack both are zero. Not at any edge, I want it to be level-triggered.
Btw, the assertion I posted earlier will not be useful in my case as it will get triggered at every posedge of sclk and I will see failures throughout my simulation. So, please suggest a better method.
Thanks