Assertion for clock gating

SystemVerilog
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2

In reply to foxtrot:
Your requirements are ambiguous.
Can you create a table or a better description of the requirements?
For example,

  • If ref = 0 and ack = 0 then …
    // or is it “if($fell(ref) and ack”, or is it "if($fell(ack) …
  • …If(…) then …
  • …

You need to clarify the antecedents. It is OK (or even better) to have multiple small assertions.
With *!refclk throughout (!refClkReq && !refClkAck) [1:$];
are you trying to say


@(posedge sclk) $fell(req) |-> !refclk throughout (!Req ##[*1:$] !Ack);

Thethroughout operator specifies that a signal (expression) must hold throughout a sequence.
*( b throughout R ) is equivalent to ( b [0:$] intersect R )
For example, in the following handshake example, a req is honored with an acknowledge within the next 4 cycles. The ack is then followed at a later time by a done control signal. However, there is one additional requirement that throughout the time between the ack and done an enable signal must be asserted to drive a tri-state bus. That assertion can be expressed as follows. Figure 2.4.6 demonstrates a timing diagram that satisfies an assertion of this property.

ap_handshake : assert property (
$rose(req) |-> ##[1:4] enable throughout (ack ##[1:$] done));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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