Assertion for check SOP signal loss

SystemVerilog
,
6

In reply to DefaultName:

You can try this :
//property declaration
property EOP_EOP_SOP(clk,SOP,EOP,valid);
@(negedge clk) ((EOP && !SOP) |=> (!(EOP && valid && !SOP) throughout EOP[->1]));
endproperty

…
//property instance
u_EOP_EOP_SOP : assert property (EOP_EOP_SOP(clk_signal,SOP_signal,EOP_signal,valid_signal)) else `uvn_error(“top”,“EOP was set twice without SOP”)