Assertion for check SOP signal loss

SystemVerilog
,
5

In reply to DefaultName:


// On this other addition, note that by itself
p_eop_sop_eop: assert property(
          eop |-> sop[->1] ##0 eop[->1]);
// it does not address the case of 2 eop, like 
//  eop ... eop ... sop ... eop 
//
// It also does not address the case of 2 sop, like 
//  sop ... sop ... eop 
// 
// My first solutions do adddress thse points.

Ben