Hello. I have interface with SOP and EOP signals. I would like to write an assertion that will control for loss SOP signal. That is the EOP signal comes again without SOP. I wrote this design: sva_sop_loss: assert property (eop |=> !eop throughout ##[*] sop) else $error(“%m”); This worked well…

In reply to ben@SystemVerilog.us : You could add p_eop_sop_eop: assert property( eop |-> sop[->1] ##0 eop[->1]); Ben

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Assertion for check SOP signal loss

SystemVerilog

DefaultName November 25, 2022, 7:19am 4

In reply to ben@SystemVerilog.us:
Thanks, Ben