In reply to aehsan:
Just looking at the syntax, 1800 defines what a property is, and one of the property expressions is:
property_expr ::=
sequence_expr |-> property_expr
From that, you deduce that the following is also legal:
sequence_expr |->
sequence_expr |-> property_expr
You have:
$fell(hready_cpu) |-> // sequence
(read_trans and (wr_trans |-> `true)) // ANDing of 2 properties
|=> $rose(hready_cpu)) // another property (followed by |=> )
That is a violation of the definition of a property
property |=> property // IS NOT a property expression
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
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