[Assertion] Dynamic Repetition

SystemVerilog
4

In reply to bdreku:
It is possible to do what you want in SystemVerilog, but not in SVA.
Specifically, you want something like


import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    bit clk, r, a=1, b=1, c=1, d=1;   
    int rpt=3, thread;
    event e_pass, e_fail, e_abcd, e_done, e_clk;  // for debug  
    let tID="My model"; 
    
    initial forever #10 clk=!clk;  
    sequence seq1; @(posedge clk) a ##1 b; endsequence 
    sequence seq2; @(posedge clk) c ##2 d; endsequence      
    
    ap_r : assert property(@(posedge clk) $rose(r) |->  
       (seq1 ##0 seq2) ##0 (seq1 ##0 seq2) ##0 (seq1 ##0 seq2));
    // Action block is not used here 

    // (seq1 ##0 seq2) ##0 (seq1 ##0 seq2) ##0 (seq1 ##0 seq2)
    task automatic t_abcd(int count); // 
       bit match=1'b1; 
       int my_thread;
       my_thread=thread; thread+=1; 
        -> e_abcd;
       repeat(count) begin : rpt1  // seq1; va ##1 b;
         //seq1:  a ##1 b
         if(match && a) match=1'b1; 
         else begin match=1'b0; disable rpt1; end 
         @(posedge clk) if(match && b) match=1'b1; 
         else begin match=1'b0; disable rpt1; end 
         // ##0 seq2: c ##2 d;
         if(match && c) match=1'b1; 
         else begin match=1'b0; disable rpt1; end 
         @(posedge clk); -> e_clk; 
         @(posedge clk);
         if(match && d) match=1'b1; 
         else begin match=1'b0; disable rpt1; end 
       end : rpt1  
       ai_3sq: assert(match) else
        `uvm_error(tID,$sformatf("%m : t_abcd FAIL, my_thread=%d", my_thread))
        if(match) -> e_pass; else -> e_fail;   
        -> e_done; 
   endtask

   always @(posedge clk) 
     fork 
       if($rose(r)) t_abcd(rpt); 
     join_none


   //ap_r_task : assert property(@(posedge clk) 
   //     $rose(r) |-> (1, t_abcd(rpt)));

 initial begin  
    bit vr, va, vb, vc, vd;
    repeat(40) begin 
    @(posedge clk) if (!randomize(vr)) `uvm_error("MYERR", "This is a randomize error") 
    r <= vr; //
    end 
    repeat(30) begin 
        repeat(2) @(posedge clk);   
        if (!randomize(vr, va, vb, vc, vd)  with 
        { va dist {1'b1:=1, 1'b0:=1};
          vb dist {1'b1:=1, 1'b0:=2};
          vc dist {1'b1:=1, 1'b0:=3};    
          vd dist {1'b1:=1, 1'b0:=1};    
        }) `uvm_error("MYERR", "This is a randomize error") 
        r <= vr; a<=va; b<=vb; c<=vc; d<=vd; 
    end 
    $finish; 
  end 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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