In reply to ben@SystemVerilog.us:
Thanks Ben.
The repetition operator checks whether a signal or a sequence repeats for given number of clock cycles.
so the (seq1 ##0 seq2)[*3] is expanded as,
(seq1 ##0 seq2) ##1 (seq1 ##0 seq2) ##1 (seq1 ##0 seq2).
But as my both the sequences advances with clock, is it ever possible to have repetition after ##0 delay instead of ##1 ?
for exa, can we use repetition operator for the following series of sequences?
(seq1 ##0 seq2) ##0 (seq1 ##0 seq2) ##0 (seq1 ##0 seq2)
PS: Theoretically this requirement doesn’t make any sense, so planning to modify the sequences to adopt the ##1 repetition delay, but being a lazy coder, just want to check if it’s possible in any case.