Assertion disable clause not working as expected

SystemVerilog
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1

Hi,

I have a mixed signal property to compare two real values every clock rising edge.
The property has an enable bit using the disable iff() clause. Which is a static value not changing during run time.
In fact its always 0.


bit EN_CHK_AVG = 0; 
property p_CHK_AVG; 
  @(posedge clk) disable iff (!EN_CHK_AVG || pfc_mode == OFF || en_gate_ctrl == 0)
    (check_value(a, b, 0, 0, "CHK_AVG", 10)); // +/- 10V tolerance
endproperty 
ap_CHK_AVG: assert property(p_CHK_AVG);

The check_value() method compares a and b, within a tolerance and/or absolute difference.
It prints a message when the comparison is not successful and returns 0.
I don’t expect any of these messages to be printed since EN_CHK_AVG is 0.

I get this output when I run it

UVM_INFO @ 416385.00000 ns: reporter [CHK_VALUE_ERR] CHK_AVG value is not close enough to expected value !
Actual value : 0.00
Expected value : 37.25
Variation (0…1) is : 0.00 [or +/-10.00]
Expected range is between 47.25 and 27.25
UVM_INFO @ 416385.00000 ns: reporter [CHK_VALUE_ERR] CHK_AVG value is not close enough to expected value !
Actual value : 0.00
Expected value : 37.25
Variation (0…1) is : 0.00 [or +/-10.00]
Expected range is between 47.25 and 27.25
ncsim> describe systemTop.pfc_mon.EN_CHK_AVG
systemTop.pfc_mon.EN_CHK_AVG…variable bit = 1’h0

The check_value message is printed twice every clk edge. However the assertion error is not triggered.
The behaviour of disable iff() seems to disable the assertion but not the code in the property.
Is this the way it’s supposed to behave?

Thanks

Damian

2

In reply to DamianS:
You are dealing with tool specific behavior as this is not legal SystemVerilog code. Please contact your vendor as this Mentor sponsored forum is not for discussing tool specific issues.

3

In reply to dave_59:

Why is it tool specific. Its a general question about a SV assertion and the disable clause

4

In reply to DamianS:

You have a method involving the sampling of real values. That is not defined in the LRM.

In any case, I do not agree with the behavior of the tool you are using, but putting a display statement inside a function as part of a boolean expression is considered a side affect and not allowed anyway.

5

Thanks for your reply.

I changed a, b and the method to integers, but I see almost the same behaviour. That is the property is executed regardless of disable clause. Only once per clock edge with integers and twice per clock in the case of reals. This is not what I expected, is my understanding of disable iff incorrect?

It seems to only disable the assertion not the property.
I can remove the print side effect from check_value() although that leaves a rather unsatisfactory error message => Assertion xxx has failed.

Anyway that doesn’t change the fact that the method is called when disabled which is not efficient.

6

I considered this as a workaround but it didn’t change the behaviour. Maybe it’s a bug in the tool I sent a message to the vendor…


property p_CHK_AVG; 
//    @(posedge clk) disable iff (!EN_CHK)
        (check_value_int(a_int, b_int, 0, 0, "CHK_AVG", 50)); // +/- 50 tolerance
endproperty 
//ap_CHK_AVG: assert property(p_CHK_AVG);

// Assert property on clk edge with condition instead of using disable iff()
always @(posedge clk)
    if (EN_CHK)
       ap_CHK_AVG: assert property(p_CHK_AVG);