ASSERTION: detects if one input is a delayed version of the other

SystemVerilog
, ,
5

In reply to gumpena@usc.edu:

Need to add

 
initial begin 
  @(posedge clk);
  while (!rose(S1) || !$fell(S1)) begin
   assert(!rose(S2) || !$fell(S2))
        else $error("S1 pulse wih no s2 pulse ");
    @(posedge clk);
   end 
end

Ben systemverilog.us